Arm Unveils Neoverse CSS N4 Platform with 128 Cores and LPDDR6 Support

Arm has officially launched its next-generation Neoverse CSS N4 "Ranger" compute subsystem platform, further strengthening its position in cloud computing and artificial intelligence infrastructure. As a key component of Arm's semi-custom chip strategy, the Neoverse CSS N4 is built on TSMC's N3P process and can integrate up to 128 Neoverse N4 cores in a single chip, making it one of the most flexible and largest compute subsystems in the Arm Neoverse family to date.

Neoverse CSS, which stands for Compute Subsystem, is a semi-custom solution Arm offers to major cloud service providers and chip design companies. Customers can freely configure core counts, cache capacity, memory systems, I/O interfaces, and chip interconnect structures on the foundation of Arm's base IP framework, allowing them to rapidly develop custom processors tailored to their needs. Over the past several years, this platform has been used by companies such as Microsoft Azure and Google Cloud for server processor development, and has also been widely adopted in data processing units from Nvidia and Intel.

According to information released by Arm, the Neoverse CSS N4 supports flexible configurations ranging from 8 to 128 cores, with a maximum frequency of 3.8GHz. In terms of system scalability, the platform not only supports single-chip configurations of up to 128 cores but can also be expanded further through multi-chiplet and multi-socket options. The platform supports the UCIe chiplet interconnect standard and allows partners to use custom interconnect technologies to build larger-scale computing systems, meeting the demands of hyperscale data centers and AI infrastructure.

The cache and memory subsystems have been significantly enhanced compared with the previous generation. The Neoverse CSS N4 supports up to 256MB of L3 cache per chip, with each core able to be equipped with up to 2MB of L2 cache, along with 64KB of L1 instruction cache and 64KB of L1 data cache. For memory, it supports DDR5 and introduces LPDDR6 support for the first time, catering to different application scenarios with varying power and bandwidth requirements. I/O capabilities have also been notably upgraded, with the new platform supporting up to 128 PCIe 7.0 or PCIe 6.0 lanes and compatibility with the CXL 4.0 standard, providing greater expansion headroom for high-performance storage devices, AI accelerators, and high-speed network interfaces.

Compared with the previous-generation Neoverse CSS N2, the new platform represents a comprehensive upgrade. The previous generation supported a maximum of 64 cores, 1MB of L2 cache per core, and 64MB of L3 cache, and offered only 64 PCIe 5.0 and CXL lanes. The Neoverse CSS N4 delivers substantial improvements in core count, cache size, I/O bandwidth, and memory support. Arm's data shows that in a configuration with 128 cores, a 3GHz operating frequency, and 2MB of L2 cache per core, the Neoverse CSS N4 achieves twice the single-socket performance of the Neoverse N3 platform, a performance-per-watt improvement of approximately 25%, and a memory bandwidth increase of about 75%.

Arm also noted that the Neoverse N-series cores and V-series cores have different positioning. The N-series is primarily aimed at energy efficiency and high-density deployment, while the V-series pursues extreme performance. Currently, Nvidia's previous-generation Grace processor uses Neoverse V2 cores, and AWS's Graviton series as well as Google Cloud's Axion project also adopt the Neoverse architecture. The N-series is more commonly used for control plane tasks, network processing, and power-sensitive computing scenarios.

In addition to launching the Neoverse CSS N4, Arm also provided an update on its AGI CPU project. This product is built on the Neoverse V3 architecture and has received deployment support from companies including Oracle, ByteDance, Meta, OpenAI, Cloudflare, and SAP. With the AGI CPU and Neoverse CSS N4, Arm is pursuing a dual-track strategy: on one hand, offering customers a highly customizable chip development platform, and on the other, delivering reference-grade server processor solutions for the AI era.