Intel High-NA EUV Cumulative Wafer Processing Exceeds 1 Million

Intel Foundry announced on September 8 that its cumulative wafer processing using high numerical aperture extreme ultraviolet (high-NA EUV) lithography has exceeded 1 million wafers. The figure encompasses equipment certification, testing, research and development, and volume production of certain product layers. The milestone was disclosed during the SPIE Photomask Technology and EUV Lithography conference held in Monterey, California. Intel stated that its high-NA EUV wafer processing volume has surpassed the combined total of all other chipmakers employing the technology worldwide.

High-NA EUV is the next-generation version of EUV lithography, with the numerical aperture increased from 0.33 in conventional EUV equipment to 0.55. This enables finer patterning on wafers and reduces the need for certain complex multiple-patterning processes. For advanced process nodes, the technology offers higher transistor density and lower manufacturing complexity, but it also entails higher equipment costs and more demanding process requirements. Intel has deployed at least three high-NA EUV lithography tools in Oregon and uses them for part of its Intel 18A process production.

Intel has not assigned the entire 18A process to high-NA EUV; instead, it has selected certain critical layers for production using this technology. These layers are also validated on conventional 0.33-NA EUV equipment to compare manufacturing performance between the two approaches. Intel said that the 18A layers produced with high-NA EUV have achieved performance equal to or better than the corresponding layers manufactured on conventional EUV platforms. Panther Lake, part of Intel's Core Ultra Series 3, is built on the 18A process. By introducing high-NA EUV on selected product layers, Intel is accumulating volume production experience without fully relying on the new equipment.

Intel Foundry stated that high-NA EUV has entered the production stage, and the company is continuously optimizing equipment settings, uptime, and manufacturing processes. Intel is also collaborating with ASML to improve the technology's maturity and will determine the extent of high-NA EUV adoption in future process nodes based on customer requirements. Additionally, Intel is promoting the development of larger photomasks.

Intel has partnered with ASML, photomask manufacturers, automation equipment suppliers, EDA software companies, materials suppliers, and other chipmakers to advance the standardization and supporting infrastructure for 6x12-inch large photomasks. The company said customers can currently use high-NA EUV with existing 6-inch photomasks, either by designing chips within the mask field or by using stitching techniques and process design kits to address larger-area manufacturing needs. Intel currently applies high-NA EUV to selected 18A layers; whether the application scope can be expanded in the future will depend on equipment throughput, production costs, yield, and customers' actual process requirements.