Intel Unveils Diamond Rapids Server CPU: 18A-P Process, Up to 256 Cores, 1.6TB/s Memory Bandwidth
Intel formally introduced its next-generation server processor, Diamond Rapids, at Hot Chips 2026. Built on the 18A-P process, the chip offers up to 256 P-cores, 1.6TB/s memory bandwidth, 128 PCIe Gen 6 lanes, and CXL 3.0 support. Compared with the previous Xeon 6 generation, core count rises by more than 50%, with significant gains in memory bandwidth and I/O capabilities. The processor targets enterprise AI agent infrastructure and competes with AMD and Arm offerings.
Intel formally unveiled its next-generation server processor, Diamond Rapids, at Hot Chips 2026. The chip is manufactured on the 18A-P process and features up to 256 P-cores, supporting 1.6TB/s memory bandwidth, 128 PCIe Gen 6 lanes, and CXL 3.0. Positioned for enterprise AI agent infrastructure, it competes with comparable products from AMD and Arm. Relative to the previous Xeon 6 generation, core count increases by more than 50%, with substantial enhancements in memory bandwidth and I/O capabilities.
Diamond Rapids introduces a Fan-out Fabric architecture that decomposes chip functionality into four modules: scalable compute building blocks, a centralized I/O and memory Fabric Hub, a unified memory fabric, and a flexible I/O fabric. Physically, the chip is assembled from 22 separate dies, including 16 core chiplets based on the Intel 18A-P process, two Fabric Hubs based on the Intel 3 process, and four base dies based on the Intel 3-T process. These components are interconnected via Foveros Direct 3D hybrid bonding and UCIe-S copper interconnects. Memory controllers are removed from the compute chiplets and integrated into the Fabric Hub to enable more flexible scaling. Each compute building block contains 16 cores, with a 3D Xbar connecting to the last-level cache on the base die. The entire chip shares 1.28GB of LLC, with each base die carrying 320MB.
In terms of core specifications, Diamond Rapids offers up to 256 P-cores based on the Panther Cove-X architecture, arranged as four compute building blocks, each containing four core chiplets. This matches the 256-core ceiling of AMD's EPYC Venice. The memory subsystem supports a 16-channel design, reaching 12,800 MT/s with MRDIMMs and 8,000 MT/s with standard DDR5, delivering peak memory bandwidth of 1.6TB/s. For I/O, the chip provides 128 PCIe Gen 6 lanes and supports CXL 3.0. Additionally, it introduces a new advanced performance extension instruction set and an enhanced version of Advanced Matrix Extensions to accelerate AI inference and matrix operations. Diamond Rapids does not support hyper-threading, a feature that will return in its successor, Coral Rapids. The platform uses an LGA 9324 socket, with a maximum TDP of 650W.
Intel is collaborating with Nvidia on a custom x86 SKU featuring an NVLink interface, which is currently in development and will be delivered to Nvidia. This processor will be integrated into Nvidia's CPU diversification strategy, while Intel will also compete with Nvidia's Vera and AMD's Venice in the data center CPU market. Diamond Rapids' mass production timeline and actual delivery performance will determine its market success.