JCET Advances High-Aspect-Ratio TSV Technology, Completes Sample Trial Production
JCET announced on August 19 that it has made significant progress in developing high-aspect-ratio advanced through-silicon via (TSV) technology and completed sample trial production with partners. The solution targets 2.5D/3D advanced packaging, silicon-based interconnection and multi-dimensional heterogeneous integration, strengthening the company's underlying process capabilities in microsystem integration and supporting system-level integration of high-computing-power and high-memory-capacity chips.
On August 19, JCET announced important progress in the research and development of high-aspect-ratio advanced through-silicon via (TSV) technology, and completed sample trial production together with partners. The TSV fabrication solution targets high-end advanced packaging applications including 2.5D/3D advanced packaging, silicon-based interconnection and multi-dimensional heterogeneous integration, and aims to strengthen the company's key underlying process capabilities in its microsystem integration platform, providing more complete and flexible one-stop manufacturing support for system-level integration of high-computing-power and high-memory-capacity chips.
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