Samsung and Qualcomm Expand Semiconductor Tie-Up on 2.1D Advanced Packaging

Samsung and Qualcomm are expanding their cooperation in semiconductors, having begun work on 2.1D advanced packaging technology with the goal of providing higher-density, higher-speed chip interconnect solutions for next-generation high-performance computing and artificial intelligence chips. As generative AI and high-performance computing advance, the volume of data a single chip must process continues to rise, and traditional packaging methods struggle to meet the demand for high-speed, large-scale data transfer between chips. AI accelerators typically need to integrate compute chips with high-bandwidth memory and other functional chips in the same package, making advanced packaging an important factor affecting AI chip performance.

One of the mainstream high-end approaches in the industry is 2.5D packaging, which usually connects multiple chips through a silicon interposer to achieve high-density signal interconnects. The silicon interposer itself is relatively costly, and as package sizes continue to grow, its manufacturing difficulty and yield pressure increase further. 2.1D packaging no longer relies on a traditional silicon interposer, instead using high-density fine lines on advanced packaging substrates to connect different chips directly. The 2.1D packaging substrate recently demonstrated by Samsung adopts this approach, using finer lines and higher-density connection structures to achieve high-performance chip interconnects without a silicon interposer. AI chips need to transmit massive amounts of data among compute chips, high-performance memory such as HBM and other chiplets, and the interconnect speed and bandwidth inside the package directly affect overall system performance.

Samsung Electro-Mechanics recently showcased 2.5D and 2.1D packaging substrates for AI accelerators. The 2.5D solution addresses warpage in large-size, high-layer-count substrates and improves high-speed signal transmission and high-density connection capability; the 2.1D solution uses fine-line and high-density connection technology to achieve direct connections between chips without a silicon interposer. Samsung Electronics has established the Multi-Die Integration Alliance, working with EDA, IP, DSP and packaging and testing companies to provide a technology system for multi-chip integration from chip design to packaging and testing. In addition to its foundry business, Samsung also has a memory business and advanced packaging capabilities.

Qualcomm has chip design experience in high-performance mobile SoCs and other computing platforms. The two companies have maintained a long-term cooperative relationship, and Qualcomm's Snapdragon chips have been produced using Samsung foundry technology. In recent years, the two companies have further expanded cooperation in mobile chips, Galaxy devices and artificial intelligence, and the scope of this cooperation has now extended to 2.1D advanced packaging. As phones, PCs and edge AI devices increasingly run large AI models, a single SoC needs to integrate more compute units, cache, NPUs and high-speed memory resources. Combining multiple chips through chiplets and advanced packaging technology can avoid relying solely on enlarging a single chip to improve performance.

As advanced processes approach physical limits, the cost and performance benefits of continuing to shrink transistor dimensions gradually decline, and the industry is relying more on chiplets, 2.5D and 3D packaging and high-bandwidth memory to achieve performance gains through system-level integration. Samsung is increasing investment in 2.1D and 2.5D while advancing glass substrate technology; compared with traditional organic material substrates, glass offers greater rigidity and dimensional stability. Samsung is also developing 3D packaging technologies including X-Cube, which shorten data transmission distances between chips by stacking them vertically and increase interconnect density per unit area.

The AI chip market currently makes extensive use of 2.5D advanced packaging based on technologies such as CoWoS, and Samsung is building alternatives through multiple technology routes including 2.1D, 2.5D, 3D and glass substrates. The importance of packaging substrates in chip integration continues to rise, as communication bandwidth between chips, signal quality, package size, manufacturing cost and yield are all directly related to the performance of AI chips.