Samsung to Build Exynos 2700 on 2nm SF2P with SbS Packaging; Peak Clock 4.20GHz

Samsung plans to use its 2nm SF2P process and SbS packaging architecture to build its next-generation flagship in-house SoC, the Exynos 2700. The chip's peak frequency will reach 4.20GHz, a significant performance increase over the previous generation Exynos 2600's 3.9GHz.

SbS stands for "Side-by-Side" packaging, Samsung's new chip integration solution based on FOWLP (Fan-Out Wafer Level Packaging). Its core is to break the traditional vertical stacking of SoC and memory chips, achieving horizontal integration. Under this architecture, the SoC main controller and DRAM memory are no longer stacked vertically, but placed side by side on the same plane, with an HPB heat spreader module covering both chips. This layout supports faster and more stable high-frequency memory, and also solves the heat accumulation problem in traditional PoP packaging where memory acts as a "blanket" over the SoC.

In traditional PoP packaging, memory chips are stacked directly on top of the SoC, but memory signals must go from the controller at the edge of the SoC, down through the package substrate, laterally around, and then back up to connect to the memory chips, resulting in many inefficient detours, vias, and corners, leading to long and tortuous signal paths, with interference and delay issues amplified under high-frequency operation. In contrast, SbS packaging can place memory chips directly at the edge of the SoC, closest to the memory controller, achieving point-to-point connections and significantly shortening data transmission distances. Based on currently available data, the Exynos 2700's memory bandwidth can achieve a 30% to 40% improvement, helping to speed up application launch times, improve multitasking smoothness, and enhance stability under heavy loads.

SbS packaging is an integrated pre-packaging solution that changes the supply chain division of labor. Before shipping the main controller, Samsung will complete the integrated side-by-side packaging and calibration of the SoC with the corresponding memory specifications, shipping the integrated module directly. Terminal manufacturers can then proceed directly with device assembly. This requires terminal manufacturers to accurately predict future memory market conditions at the product planning stage, with almost no room for error. Terminal manufacturers may only use SbS packaging for ultra-flagship models, while ordinary high-end models will continue to use traditional PoP packaging.

Samsung is one of the few companies that possesses in-house memory production capabilities, high-end chip design capabilities, and advanced wafer packaging lines, achieving full-chain autonomy from memory production to chip design to packaging and testing. This allows Samsung to adjust the memory specifications and capacity allocation of SbS packaged chips in real time according to new product plans and market price fluctuations, precisely controlling inventory risk. While other manufacturers are constrained by supply chain shortcomings, Samsung can dominate the pace of product iteration.